1. Field of the Invention
The present invention relates generally to a semiconductor chip package and a method for manufacturing the same, and more particularly, to a wafer level chip scale package that may include a gap and a method for manufacturing the same.
2. Description of the Related Art
The electronic industry may seek methods, techniques and designs that provide electronic products that may be smaller, lighter, faster, more efficient, operate at higher speeds, provide multiple functions and/or result in improved performance (for example), at an effective cost. One area of development may be package assembly techniques that may provide for packages such as wafer level chip scale packages (WLCSPs), for example.
FIG. 1 is a cross-sectional view of an example of a conventional WLCSP 110.
Referring to FIG. 1, the WLCSP 110 may include a semiconductor chip 111 that may have an electrode pad 112. A passivation layer 113 may be provided on the semiconductor chip 111. The passivation layer 113 may expose the electrode pad 112. A first insulating layer 115 may be provided on the passivation layer 113. The first insulating layer 115 may expose the electrode pad 112. A seed metal layer 117 may be provided on the first insulating layer 115 and the electrode pad 112. A redistribution line 123 may be provided on the seed metal layer 117. A second insulating layer 125 may be provided on the first insulating layer 115 and the redistribution line 123. The second insulating layer 125 may expose a portion of the redistribution line 123. The exposed portion of the redistribution line 123 may provide a bump land 123a. A solder bump 129 may be provided on the bump land 123a. The electrode pad 112 of the semiconductor chip 111 may be electrically connected to the solder bump 129 via the redistribution line 123.
The conventional WLCSP 110 may produce chip scale packages at a wafer level. However, the wafer level chip scale package 110 may not have a substrate between the semiconductor chip 111 and the solder bump 129. This may reduce solder joint reliability when the WLCSP 110 may be mounted on another device (e.g., a main substrate and/or a module substrate). For example, cracks may occur at a solder joint due to stresses which may be caused by (for example) a difference in coefficients of thermal expansion (CTE) between the semiconductor chip 111 and the main substrate and/or the module substrate.
In an effort to avoid such shortcomings, a WLCSP 210 may be provided as shown in FIG. 2.
Referring to FIG. 2, the WLCSP 210 may have a metal post 227. The metal post 227 may be provided on a bump land 223a and may be embedded in a solder bump 229. The metal post 227 may support and/or secure the solder bump 229. The metal post 227 may reduce the likelihood of cracks, which may occur at a solder joint, thereby improving solder joint reliability.
However, fabricating the WLCSP 210 may involve additional processes for forming the metal post 227, thereby resulting in a more complicated manufacturing process. For example, after forming the second insulating layer 225, a series of processes may follow, such as processes for applying, exposing and developing a photoresist, forming a metal post and removing the photoresist. Therefore, the manufacture of the WLCSP 210 may consume increased time and costs.
Another effort to avoid the solder joint shortcoming may involve providing a WLCSP 310, as shown in FIG. 3.
Referring to FIG. 3, the WLCSP 310 may have an air cavity 327. The air cavity 327 may be provided under a bump land 323a. When the wafer level chip scale package 310 may be mounted on a main substrate and/or a module substrate (for example), the air cavity 327 may absorb stresses, which may occur due (for example) to a difference in CTEs between a semiconductor chip 311 and the main substrate and/or the module substrate. Therefore, solder joint reliability may be improved. Further, since air may have a low dielectric constant, the pad capacitance may be reduced and the signal transmission speed may be improved.
However, fabricating the WLCSP 310 may involve additional processes for forming the air cavity 327, thereby resulting in a more complicated manufacture process. For example, a process for forming the air cavity 327 may include a series of processes, such as processes for removing a first insulating layer, coating a polymer, leveling the polymer, forming a seed metal layer and a metal connection pad, and removing the polymer. Therefore, the manufacture of the WLCSP 310 may consume increased time and costs.